The present invention relates to a graphics system, and more particularly, to an apparatus and method for controlling early depth processing and post depth processing.
As known in the art, graphics processing is typically carried out in a pipelined fashion, with multiple pipeline stages operating on the data to generate the final rendering output (e.g., a frame that is displayed). Many graphics processing pipelines now include one or more programmable processing stages, commonly referred to as “shaders”, which execute programs to perform graphics processing operations to generate the desired graphics data. For example, the graphics processing pipeline may include a vertex shader and a pixel (fragment) shader. These shaders are programmable processing stages that may execute shader programs on input data values to generate a desired set of output data for being further processing by the rest of the graphics pipeline stages. The shaders of the graphics processing pipeline may share programmable processing circuitry, or may be distinct programmable processing units.
In addition to the vertex shader and the pixel shader, early depth (Early-Z) processing and post depth (Post-Z) processing are features supported by many graphics processing units (GPUs). The Early-Z processing stage is placed before a pixel shading stage in the pipeline, and the Post-Z processing stage is placed after the pixel shading stage in the pipeline. If one of the Early-Z processing and the Post-Z processing indicates that a pixel is behind a geometry (i.e., the pixel is invisible), the following processing of the pixel can be omitted to save the system resource. However, if a conventional GPU wants to use the Early-Z processing to remove invisible pixels before the invisible pixels enter the pixel shading stage, it must flush the pipeline when switching from the Post-Z processing to the Early-Z processing to maintain data coherency. Such “flush event” requires several waiting cycles and thus degrades the rendering performance.